Modern memory integrated circuits, particularly read/write circuits such as static random access memories (SRAMs) and dynamic random access memories (DRAMs), are becoming quite large in physical size and in the density of memory locations therein. For example, SRAMs with 2.sup.20 addressable locations and DRAMs with 2.sup.22 addressable locations are now readily available. Even with submicron feature sizes, the physical size of the integrated circuit chip containing such memories can be as large as on the order of 180 kmil.sup.2. In addition, many complex microprocessors now include significant amounts of on-chip memory, such as 64 kbytes or more of read-only memory and 64 kbytes or more of random access memory. The physical chip size of some of these modern microprocessors may be as large as on the order of 250 kmil.sup.2.
It is well known that as the minimum feature size in integrated circuit chips becomes smaller, the size of defect that can cause a failure (i.e., the size of a "killing" defect) also shrinks. As a result, especially with large chip sizes, it is more difficult to achieve adequate manufacturing yield as the size of a killing defect reduces. In order to reduce the vulnerability of a relatively large integrated circuit chip to a single small defect, modern integrated circuits utilize spare rows and columns that can be used to replace defective rows and columns, respectively, in the memory portion of the circuit. Substitution of one of the spare rows or columns is conventionally accomplished by the opening of fuses (or closing of antifuses, as the case may be) in decoder circuitry, so that access is made to the spare row or column upon receipt of the address for the defective row or column in the primary memory array. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses.
Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51. An example of a conventional redundancy decoder is described in U.S. Pat. No. 4,573,146, issued Feb. 25, 1986, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference.
In most memories containing redundant elements, however, the time required to access a redundant memory cell is longer than that required to access a memory cell in the primary array. Accordingly, the worst case access time for the memory is generally degraded by the enabling of redundant elements. It has been observed that a significant portion of the access time degradation is due to additional delays in the decoders associated with the redundant elements, which compare the received address value against the programmed address value to which the redundant element is to respond (i.e., the address of the replaced primary array element).
Referring now to FIG. 10, a conventional redundancy decoder will now be described. As is well known, each redundant element is associated with a decoder which has an address value programmed thereinto by fuses; the received address is compared against this programmed value and, if matching, the redundant element is to be enabled. The conventional decoder of FIG. 10 is a redundant column decoder, and includes a summing NAND gate 104 which receives inputs from decoder blocks 102 and from enable block 100; the output of NAND gate 104 is connected to an input of NOR gate 106 which also receives inputs on line HALFSEL (inverted by inverter 103) and line CEc. Line HALFSEL indicates, with a high level, that a row address has been received that corresponds to the portion of the array served by the redundant column associated with this decoder; line CEc indicates, with a low level, that the circuit is enabled. In this conventional decoder, a high logic level at the output of NOR gate 106 on line RDSEL indicates that the redundant column associated with the decoder of FIG. 10 is to be selected, as the address received by the memory matches that for which fuses have been opened (and thus each of the inputs to NAND gate 104 is at a high level).
Enable block 100 in this conventional decoder includes fuse 110 connected between the V.sub.cc power supply voltage and the drain of transistor 112, which is connected to the input of inverter 111. The source of transistor 112 is connected to ground, and the output of inverter 111 is connected to the gate of transistor 112 and, via line EN, to an input of summing NAND gate 104. In operation, fuse 110 is opened to enable redundancy, in which case the input of inverter 111 will leak to ground due to junction leakage at transistor 112; line EN, at the output of inverter 111, will go high, turning on transistor 112 to latch this condition. Summing NAND gate 104 will thus respond to the state of lines M0 through M3 at the remainder of its inputs, received from decoder blocks 102.
Decoder blocks 102.sub.0 through 102.sub.3 receive true and complement column address inputs CA0t, CA0c through CA2t, CA2c, and true and complement predecoded signals BLKt, BLKc, respectively. Each decoder block 102 includes a fuse 114 connected between V.sub.cc, on one hand, and the drain of transistor 106 and the input of inverter 105, on the other hand; the source of transistor 106 is connected to ground and the gate of transistor 106 is connected to the output of inverter 105. In each decoder block 102, inverter 107 has its input connected to the output of inverter 105. The output of inverter 107 is connected to the n-channel transistor of pass gate 108t and the p-channel transistor of pass gate 108c, while the output of inverter 105 is connected to the p-channel transistor of pass gate 108t and the n-channel transistor of pass gate 108c. Pass gate 108t receives the true address input (e.g., CA0t in decoder block 102.sub.0) and pass gate 108c receives the complementary address input (e.g., CA0c in decoder block 102.sub.0); the other sides of pass gates 108t, 108c in decoder blocks 102.sub.0 through 102.sub.3 are connected together and to an input of summing NAND gate 104 via lines M0 through M3, respectively.
In operation, the address value to which the decoder is to respond by driving line RDSEL high is determined by the state of fuses 114 in decoder blocks 102. For example, if fuse 114 in decoder block 102.sub.0 is left intact, the output of inverter 105 is low and the output of inverter 107 is high, turning on pass gate 108t and turning off pass gate 108c, thus allowing a high level on line CA0t to drive line M0 high. Conversely, if fuse 114 is opened, the output of inverter 105 will be high and the output of inverter 107 will be low, turning off pass gate 108t and turning on pass gate 108c; a high level on address line CA0c will thus drive a high level on line M0 to NAND gate 104. The address value to which the decoder is to respond is thus determined by which fuses 114 are opened in the decoder circuit.
While the decoder circuit of FIG. 10 provides good functionality, performance degradation has been observed to be due to this design. In particular, the relatively large number of transistors (e.g., nine per decoder block) should be noted, as each decoder block includes a fuse 114 connected in similar manner as that in enable block 100. Furthermore, the presence of enable block 100 requires an additional series pull-down device in summing NAND function 104 (when constructed in the conventional fashion), slowing its performance.
In addition, the switching time of the address inputs to the decoder blocks is adversely affected by unbalanced loading effects, as one of the input address lines will see a junction capacitance and conducting gate capacitance of its pass gate and the gate capacitance of an input of NAND gate 104 while the other will see only the junction capacitance of its non-conducting pass gate. The performance of the decoding operation is thus adversely affected by relatively large loads to be driven by one line, and by unbalanced loads on the complementary address lines.
It is therefore an object of the present invention to provide an integrated circuit having a redundant decoder with minimal performance degradation.
It is another object of the present invention to provide such a circuit in which complementary inputs to the redundant decoder see balanced loading.
It is another object of the present invention to provide such a circuit in which fewer transistors are required in the implementation of the decoder.
It is therefore another object of the present invention to provide such a circuit in which the performance loss in accessing a redundant column is minimized or eliminated.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.